FIG. 1 shows a schematic circuit diagram illustrating a typical image sensor array at 10. The array 10 is formed on a substrate 12, and includes an active area 14 having a two-dimensional array of pixels 16 arranged in rows and columns. Each of the pixels 16 is fabricated on the substrate 12, which may be formed as a semiconductor substrate or a glass substrate (oriented in the plane of the drawing). While FIG. 1 only shows four pixels 16, it will be understood that the array 10 may include any number of pixels. Each of the pixels 16 is connected to a corresponding one of a plurality of gate lines 18, and to a corresponding one of a plurality of data lines 20. Each pixel 16 includes: a switching device 22; and a photo-sensitive cell 24 having a first terminal connected to a corresponding one of a plurality of voltage bias lines 28 to receive a bias voltage signal, VBIAS. The switching device 22 may be implemented as a diode, a transistor or any other switching device. In the depicted example, the switching device 22 is a switching transistor including: a gate 30 connected to a corresponding one of the gate lines 18; a source 32 connected to a second terminal of the corresponding photo-sensitive cell 24 in the pixel; and a drain 34 connected to a corresponding one of the data lines 20. For certain applications, the switching transistor 22 may be implemented as an amorphous silicon (“a-Si”) thin-film-transistor (“TFT”). The switching transistor 22 in each pixel provides for switching the pixel 16 on and off under control of the corresponding gate line 18 that is connected to the gate 30 of the switching transistor 22.
During operation, the photo-sensitive cell 24 converts radiation (e.g., light or X-ray) into an electrical charge that may be stored, and ultimately converted into an electrical signal transmitted via a corresponding one of the data lines 20. The switching transistor 22 controls the charge read out of each photo-sensitive cell 24. Commonly, the photo-sensitive cell 24 is implemented as a photo-diode.
It has been observed that most common switching transistors 22, including a-Si TFT's, are sensitive to electro-static discharge (“ESD”). ESD events often occur during fabrication and later assembly of image sensor arrays. Therefore, ESD protection is needed for achieving yield and robustness in fabrication of image sensor arrays.
ESD-induced artifacts present a significant quality concern in the fabrication of image sensor arrays 10 formed on insulating substrates 12. Small variations in the threshold voltage of the switching transistors 22 caused by localized discharges to the surface of an image sensor array can lead to visible artifacts in the charge image which is produced when the array of pixels 16 addressed by these switching transistors is read out. Prior art has focused on protecting the array 10 through guard rings encircling the array and protection to the gate lines 18, such as shorting bars, back-to-back TFTs, and other protection diode structures connected to the periphery of each array. See, e.g., U.S. patent application Ser. No. 11/019,739, published May 4, 2006. These approaches provide protection from charging of the gate lines 18 during fabrication and assembly of an image sensor array 10. However, as explained below, these systems and methods do not provide adequate ESD protection for image sensor arrays during stages of fabrication prior to formation of the data lines 20 and voltage bias lines 28.
ESD events may occur during many different stages of the manufacture of image sensor arrays 20. One point in the fabrication process for image sensor arrays which has proven to be insufficiently protected from ESD events is the photolithographic patterning of the interlayer dielectric into via contact holes. This point in the process poses a unique vulnerability which is not obvious to those of ordinary skill in the art. When forming a switching transistor for an active matrix liquid crystal display (“AMLCD”), a fabrication process typically involves: depositing and patterning a gate electrode; depositing chemical vapor deposition (“CVD”) layers to form a gate dielectric (e.g., Silicon Nitride), a semiconducting layer (e.g., amorphous silicon (“a-Si”)), and etch stopper (typically Silicon Nitride) or doped contact (typically n+ a-Si) layers; and depositing a top metal to form the data lines and voltage bias lines. In this sequence, the switching transistor is vulnerable to localized ESD when the a-Si and n+ layers are patterned into individual islands and prior to interconnection with the top metal.
In the case of an image sensor array using TFT's for switching transistors, additional thick interlayer dielectric is added to isolate the data lines 20 from the underlying gate lines 18 to minimize capacitance. A typical process includes depositing and etching the gate metal, depositing CVD layers to form the switching transistors (e.g., TFTs), patterning an island in the etch stopper layer (leaving the a-Si continuous), and then depositing a sequence of a doped n+ a-Si layer, a chrome (“Cr”) layer, a n+ doped-intrinsic-p+ doped (“nip”) layer sequence, and an indium-tin-oxide (“ITO”) transparent conducting layer. In this part of the process, the a-Si is shunted by n+, Cr, and the top surface is shunted by ITO, rendering the plate insensitive to ESD. Once the photo-sensitive cells are patterned and the source and drain electrodes are patterned, the switching transistors are isolated and become vulnerable to ESD. At this point, a thick interlayer dielectric (e.g., Silicon Oxynitride) is deposited and patterned into vias. A top layer of metal is then deposited and patterned into the data lines 20 and bias lines 28, and then a top passivation layer of silicon oxynitride is deposited and patterned.
FIG. 2 shows a cross section of a pixel 38 of a partially fabricated image sensor array structure 40 as it exists during one of the above-described stages of fabrication that has proven to be insufficiently protected from ESD events. The pixel 38 of the partially fabricated image sensor array 40 includes: an at least partially fabricated switching transistor structure 42 formed over a substrate 12; an at least partially fabricated photo-sensitive cell structure 44 formed over the substrate 12; and a dielectric interlayer 46 formed over the structures 42 and 44. The stage of fabrication depicted in FIG. 2 is prior to photolithographic patterning and etching of the dielectric interlayer 46 to form via contact holes for connecting the data lines and voltage bias lines. During the stage shown in FIG. 2, the pixels 38 are electrically isolated from each other because the data lines 20 and voltage bias lines 28 have yet to be formed. As will be explained below, the image sensor array 40 is particularly susceptible to ESD damage while it is in the state of partial fabrication depicted in FIG. 2.
As will be understood by those of ordinary skill in the art, the switching transistor structure 42 and the photo-sensitive cell structure 44 may be formed in accordance with many different prior art processes. By way of example, the switching transistor structure 42 may include: a gate electrode 50 (e.g., a metal gate comprising titanium-tungsten (“Ti—W”, Ta, or Mo)) formed over the substrate 12; a gate dielectric 52 (e.g., a layer of silicon nitride) formed over the gate electrode 50 and over the substrate 12; a layer of amorphous silicon (“a-Si”) 54 formed over the gate dielectric 52, and above the gate electrode 50; an etch stopper 56 (e.g., a layer of silicon nitride or a layer of n-doped amorphous silicon) formed over the layer of amorphous silicon 54; a source electrode 58 (e.g., a layer of n+ a-Si or microcrystalline Si covered with a contact metal like chrome) formed over the gate dielectric 52, adjacent the etch stopper 56 and amorphous silicon 54; and a drain electrode 60 (e.g., a layer of n+ a-Si or microcrystalline Si covered with a contact metal like chrome) formed over the gate dielectric 52, and adjacent the etch stopper 56 and amorphous silicon 54. As will be understood by those of ordinary skill in the art, a switching transistor structure 42 may be formed in accordance with many different techniques, and may be structured in many different ways. As also will be understood by those of ordinary skill in the art, and by way of example only, the partially fabricated photo-sensitive cell structure 44 may include: an n-type doped amorphous silicon layer 61 formed over a portion of the source electrode 58; an intrinsic amorphous silicon layer 62 formed over the layer 61; a p-type doped amorphous silicon layer 64 formed over the layer 62; and a top electrode layer 66 formed over the layer 64. Commonly, the top transparent electrode layer 66 is formed from indium-tin-oxide (“ITO”) or indium-zinc-oxide (“IZO”). However, other materials may be used to form the top electrode layer. The source electrode 58 of the switching transistor also serves as a bottom electrode of the photo-sensitive cell structure 44.
FIG. 3 shows a simplified perspective view at 70 of a partially fabricated image sensor array structure 40 as it exists during one of the above-described stages of fabrication that has proven to be insufficiently protected from ESD events. As shown in FIG. 3, the fabricated image sensor array structure 40 includes an array of pixels 16, each including the at least partially fabricated switching transistor and photo-sensitive cell structures formed over the substrate 12. In the depicted stage of fabrication, gate lines 18 have been formed, but the data lines 20 (FIG. 1) and voltage bias lines 28 (FIG. 1) have yet to be formed. During this stage of the fabrication process, the switching transistor structures 42 are electrically isolated. Therefore, the above-described prior art ESD protection measures (e.g., use of protection diode structures) are generally not sufficient to protect the partially fabricated image sensor array structure 40 from ESD events.
In accordance with typical prior art methods for fabricating image sensor arrays, the partially fabricated image sensor array structure 40 (FIGS. 2 and 3) is subjected to subsequent processing steps including photolithographic patterning of the dielectric interlayer 46 (FIG. 2) to create contact holes for purposes of connecting the drain electrode 60 (FIG. 2) and top electrode layer 66 (FIG. 2) to data lines and voltage bias lines respectively. During subsequent processing steps performed on the array 40 (e.g., the aforementioned patterning of the interlayer dielectric 46 to create via contact holes), it has been found that electrostatic discharges to either the front surface 11 or back surface 13 of the insulating substrate 12 can cause localized damage to the switching transistor structures 42 (FIG. 2), which leads to significant ESD artifacts. This type of damage can be caused during fabrication processing steps in which the substrate 12 is charged up to a high potential and moves close to a metallic point somewhere in the fabrication process, causing an electrostatic shock to the surface of the substrate 12.
A typical image sensor array fabrication processing line includes multiple process stations and various types of apparatus for moving the substrate 12 from one station to another. Referring to FIG. 3, such apparatus may include a pin 71, which lifts the substrate 12 from a platen (not shown). Often, the pin 71, platens and other levers used in the process stations are made of dissimilar materials. In such environments, arcing 72 may occur to the back side 13 of the substrate 12 when it is removed from lift pin 71 and transferred from one process station to the next. If the switching transistors 42 are electrically isolated, as they are during the patterning of the interlayer dielectric 46 (FIG. 2), then the charge induced on the back side 13 of the substrate 12 will cause high potentials on the top surface 11 and cause localized damage to the switching transistors 42 (FIG. 2) proximate the discharge event.
Due to the insulating nature of the substrate 12 and the fact that the pixels 16 are electrically isolated prior to top metal interconnection, any discharge 72 to the back surface 13 of the substrate 12 is localized to the immediate vicinity of the discharge event. As explained, such events can occur during typical fabrication processing steps in which the substrate 12 separates from a dissimilar material and develops tribo-electric charge. If not adequately discharged by ionizers, the substrate 12 can charge up to 10-20 kV surface potential, and thereby become highly vulnerable to ESD events.
FIG. 4 shows a charge image of an image sensor array at 78 having ESD induced artifacts 79. Often, these artifacts are caused by localized discharges to the surface of the image sensor array during various fabrication steps such as those described above.
FIG. 5 shows a schematic circuit diagram of an equivalent circuit for modeling the response of one of the pixels 38 (FIG. 2) to a triboelectric charging event 72 localized at the back surface 13 of the substrate 12. The equivalent circuit includes: a first capacitor 84, having a first capacitance value C1, connected between a gate node 85 representing the gate electrode 50 (FIG. 2) and a source node 86 representing the source electrode 58 (FIG. 2); and a second capacitor 88, having a second capacitance value C2 that is much greater than the first capacitance value C1, connected between the source node 86 and a node 90 representing the top electrode layer 66 (FIG. 2). The first capacitance value C1 represents the capacitance between the gate electrode 50 (FIG. 2) and the source electrode 58 (FIG. 2). Note that in the unprotected case, the source node 86 representing the source electrode 58 (FIG. 2) is electrically isolated in the partially fabricated image sensor array 40. The second capacitance value C2 represents the capacitance between the source electrode 58 (FIG. 2) and the top electrode layer 66 (FIG. 2). The voltage value V0 represents the voltage between the gate electrode 50 (FIG. 2) and the back side 13 (FIG. 2) of the substrate. The voltage value Vgd represents the voltage between the source electrode 58 (FIG. 2) and the gate electrode 50 (FIG. 2).
When the pixel 38 (FIG. 2) of the partially fabricated image sensor array 40 (FIG. 2) is subjected to a tribo-electric charging event 72 (FIG. 3) applied to the back side 13 of the substrate, the back side 13 can be charged to a high voltage. When the substrate separates from a smooth surface, the back side 13 of the substrate may be charged to a voltage that is in the approximate range of 10-20 kV. Both the source electrode 58 (FIG. 2) and the gate electrode 50 (FIG. 2) will have the same electrical potential (or voltage) if there is no grounded conductor close to the substrate. Referring again to FIG. 3, when a grounded conductive pin 71 is close to the back side 13 of the substrate, the “gate voltage” (i.e., the voltage at the gate electrode 50 (FIG. 6) relative to the drain electrode 60 of the switching transistor) won't drop much since the gate line 18 is long and has a relatively high capacitance compared to an individual pixel. The “voltage of the diodes” (i.e., the voltage between the source electrode 58 and gate electrode 50) of one or more switching transistors around the pin 71 will drop substantially. The final voltage on the diode is determined by the ratio of “pin-diode capacitance” (i.e., the capacitance between the top electrode 66 and the source electrode 58, which is the capacitance of the nip diode structure 44) and the “diode-gate capacitance” (i.e., the capacitance between the source electrode 58 and gate electrode 50 of the switching transistor) as a voltage divider. Switching transistors 44 (FIG. 2) around the pin will see a voltage across the gate electrode 50 (FIG. 2) and source electrode 58 (FIG. 2). This voltage can be as high as several hundred volts and can stress the switching transistors 44 (FIG. 2) and create stress marks. Similarly, voltage charging to the top surface of the plate will cause the top electrode 66 to capacitively induce voltage across the gate electrodes 50 and drain electrodes 60 of the switching transistors, also leading to ESD damage. The improvements in this invention also address ESD caused to the top side of the dielectric interlayer 46.
When a pixel of the partially fabricated image sensor array 40 (FIG. 2) is subjected to the tribo-electric charging event 82 applied to the back side 13 of the substrate 12 proximate the pixel 38, the source electrode 58 (FIG. 2) is charged to a high voltage Vgd that is approximately equally to Vo. In this unprotected case, the tribo-electric charging event 82 causes variations in the threshold voltage of the switching transistor 42 (FIG. 2), which can lead to the visible artifacts 79 (FIG. 4) in the image sensor array when the array of pixels addressed by these switching transistors is read.
One prior art method for mitigating this problem is to provide a conducting film (e.g., ITO or other thin metal) on the back side 13 of the substrate 12, which will spread out the charge caused by ESD events over the entire plate surface and prevent localized image artifacts. However, this prior art solution has the disadvantage that certain dry etch tools used to pattern the interlayer dielectric 46 (FIG. 2) rely on an electrostatic chuck to provide adequate thermal contact and cooling during the etch process. Such electrostatic chucks can only be used with insulating substrates and do not provide adequate clamping forces when the back side 13 of the substrate is coated with a conducting metal. This means that the backside metal may need to be etched off (e.g., a wet etch process) prior to dry etching the vias, which adds extra process complications. Therefore, the prior art method adds undesirable complexities to the fabrication processes.
Accordingly, it is an object of the present invention to provide a method and apparatus for fabricating an image sensor array that reduces the potential for creating ESD-induced artifacts during stages of the fabrication process when the partially fabricated switching transistor structures in the pixels are electrically isolated from each other. As an example, it is an object of the present invention to provide a method and apparatus for fabricating image sensor arrays that reduces the potential for creating ESD-induced artifacts during photolithographic patterning of the interlayer dielectric to create contact holes.
It is a further object of the present invention to provide a method and apparatus for fabricating image sensor arrays that reduces the potential for creating ESD-induced artifacts without adding any extra process complications.